1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to a system-on-a-chip integrated circuit device including a programmable logic block, at least one user non-volatile memory block, and analog circuits on a single semiconductor integrated circuit chip, flip chip, face-to-face, or other multiple die configuration.
2. Background
Field-programmable gate array (FPGA) integrated circuits are known in the art. An FPGA comprises any number of logic modules, an interconnect-routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.
An FPGA includes an array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. Programmable buses link the cells to one another. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of multiple variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain a plurality of flip-flops. Two types of logic cells found in FPGA devices are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
An FPGA circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers referred to as input/output ports (I/Os). Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis. The input/output ports provide the access points for communication between chips. I/O ports vary in complexity depending on the FPGA.
Recent advances in user-programmable interconnect technology have resulted in the development of FPGAs which may be customized by a user to perform a wide variety of combinatorial and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum et al. The architecture employed in a particular FPGA integrated circuit will determine the richness and density of the possible interconnections that can be made among the various circuit elements disposed on the integrated circuit and thus profoundly affect its usefulness.
Traditionally, FPGAs and other programmable logic devices (PLDs) have been limited to providing digital logic functions programmable by a user. Recently, however, FPGA manufacturers have experimented with adding application specific integrated circuit (ASIC) blocks onto their devices (See, e.g., U.S. Pat. No 6,150,837). Such ASIC blocks have included analog circuits (see U.S. Pat. No. 5,821,776). In addition, ASIC manufacturers have embedded programmable logic blocks in their devices to add programmable functionality to otherwise hardwired devices (See, e.g., devices offered (or formerly offered) by Triscend Corporation, Adaptive Silicon Inc., and Chameleon Systems.
Programmable logic devices with clock-conditioning circuitry including a phase lock loop circuit (PLL) are known in the art, such as FPGAs (see, e.g., the Accelerator product available from Actel Corporation, Mountain View, Calif.), and CPLDs (see U.S. Pat. No. 6,272,646 to Rangasayee et al.). Programmable logic devices such as FPGAs, however, do not typically include an on-chip crystal oscillator circuit or an RC oscillator circuit.
System on a chip devices with analog circuitry; programmable logic, such as registers for configuring and selecting the other circuitry on the device, and an on-chip crystal oscillator circuit are known (see, e.g., U.S. Pat. No. 5,563,526 to Hastings and U.S. Pat. No. 6,614,320 to Sullam). Although the system on a chip disclosed by Sullam includes a PLL circuit and a selectable clock signal (32 KHz or 24 MHz), the clocking circuitry is not programmable to output multiple clock frequencies along a broad spectrum of frequencies, according to user needs. The PLL disclosed in Sullam is used to provide a precise clocking signal, but is not configurable to synthesize arbitrary clock frequencies.
While these devices contain “programmable logic,” it is not logic of the type that can manage the overall operation of the system on a chip device, but logic that functions as registers and configuration bits to select various circuits and make selected connections on the system on a chip devices. The logic is not of a sufficient size or density or complexity to be programmed to perform most any arbitrary function that might be required by a complex user circuit design to be programmed into the system on a chip device. Furthermore, the programmable logic of the known system on a chip devices described above cannot function as the master control of the system on a chip device (see, e.g., Sullam, where a microcontroller functions as the master control of the device). In addition to Sullam, other known system on a chip devices have included a real time clock (see, e.g., U.S. Pat. Nos. 5,687,325 and 6,260,087 to Chang). The real time clock disclosed in the system of Chang, however, functions to initiate DRAM refresh cycles.